Method for low temperature bonding and bonded structure

ABSTRACT

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. One etching process The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO 2 . The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to bonding of materials at roomtemperature and, in particular, to bonding of processed semiconductormaterials, such as integrated circuit or device substrates, havingactivated surfaces to achieve high bonding strength adequate forsubsequent fabrication and/or a desired application.

[0003] 2. Background of the Invention

[0004] Direct room temperature bonding generally produces weak van derWaals or hydrogen bonding. Annealing is typically required to convertthe weak bond to a stronger chemical bond such as a covalent bond. Otherwafer bonding techniques including anodic and fusion typically requirethe application of voltage, pressure and/or annealing at elevatedtemperature to achieve a sufficient bond strength for subsequentfabrication and/or the desired application. The need to apply voltage,pressure or heat has significantly limited wafer bonding applicationsbecause these parameters can damage the materials being wafer bonded,give rise to internal stress and introduce undesirable changes in thedevices or materials being bonded. Achieving a strong bond at lowtemperatures is also critical for bonding of thermally mismatched orthermally sensitive wafers including processed device wafers.

[0005] Ultra high vacuum (UHV) bonding is one of the approaches toachieve a low or room temperature strong bond. However, the bondingwafers still have to be pre-annealed at high temperatures, forinstance >600° C. for silicon and 500° C. for GaAs, before cooling downto low or room temperature for bonding. Furthermore, the UHV approachdoes not generally work on commonly used materials, for example, inSiO₂. It is further also expensive and inefficient.

[0006] Adhesive layers can also be used to bond device wafers to avariety of substrates and to transfer device layers at low temperatures.However, thermal and chemical instability, interface bubbles, stress andthe inhomogeneous nature of adhesive layers prevent its wideapplication. It is thus highly desirable to achieve a strong bond atroom temperature by bonding wafers in ambient without any adhesive,external pressure or applied electric field.

[0007] Low vacuum bonding has been explored as a more convenientalternative to UHV bonding but a bonding energy comparable to the bulksilicon fracture energy using bonded bare silicon wafer pairs has onlybe achieved after annealing at ˜150° C. For oxide covered silicon waferpairs annealing at ˜300° C. is required to obtain a high bond energy. Ithas not been possible to obtain high bonding energies in bonded materialusing low vacuum bonding at room temperature.

[0008] A gas plasma treatment prior to bonding in ambient is known toenhance the bonding energy of bonded silicon pairs at low or roomtemperature. See, for example, G. L. Sun, Q. -Y. Tong, et al., J. dePhysique, 49(C4), 79 (1988); G. G. Goetz, Proc.of 1st Intl. Symp. onSemicond. Wafer Bonding: Science, Technol. and Applications, TheElectrochem. Soc., 92-7, 65 (1992); S. Farrens et al., J. Electroch.Soc., 142,3950 (1995) and Amirffeiz et al, Abstracts of 5th Intl. Symp.on Semi. Wafer Bonding: Science, Tech. and Appl., The ElectrochemicalSociety, 99-2, Abstract No. 963 (1999). Although these treatments haveincreased the bond energy obtainable at low or room temperature, theyhave only been demonstrated with planar silicon wafers or with siliconwafers using a plasma process that results in oxide being grown on thewafers during the plasma process. Moreover, these treatments have onlybeen used to increase the bond energy by charging or damaging thesurface. Furthermore, these treatments have not been used or shown to beapplicable to deposited dielectrics or other materials.

[0009] Obtaining low or room temperature bonding with a method that isnot only applicable to planar silicon and grown oxide surfaces butfurther to deposited materials and non-planar surfaces with planarizeddeposited materials will allow generic materials, including processedsemiconductor wafers, to be bonded with minimal damage for manufacturingpurposes. Such a method based on etching and chemical bonding isdescribed herein.

SUMMARY OF THE INVENTION

[0010] It is an object of the invention to provide a method for bondingmaterials at low or room temperature.

[0011] It is another object of the invention to bond materials bycleaning and activating the bonding surfaces to promote chemical bondformation at about room temperature.

[0012] It is a further object of the invention to provide a bondingmethod to bond any solid state material such as processed device orintegrated circuit wafers or thermally sensitive or mismatched materialsat or about room temperature.

[0013] It is further object of the invention to provide a bonding methodto bond processed device or integrated circuit wafers of different typesof devices or different technologies, and transfer a layer of devices orcircuits at or about room temperature.

[0014] It is another object of the invention to enable a direct waferbonding method that does not require annealing to achieve a requiredbond strength.

[0015] It is a further object of the invention to provide a methodwhereby diverse materials including those with non-planar surfaces anddeposited materials can be planarized and bonded.

[0016] These and other objects are achieved by a method of bondinghaving steps of forming first and second bonding surfaces, etching thefirst and second bonding surfaces, and bonding together at roomtemperature the first and second bonding surfaces after said etchingstep. The etching may include etching the first and second bondingsurfaces such that respective surface roughnesses of the first andsecond bonding surfaces after said etching are substantially the same asrespective surface rouglnesses before said etching. The surfaceroughness may be in a range of 0.1 to 3.0 nm.

[0017] The bonding surfaces may be the surface of a deposited insulatingmaterial, such as silicon oxide, silicon nitride or a dielectricpolymer. The bonding surface may also be the surface of a silicon wafer.Silicon wafers, using either the surface of the wafer or a depositedmaterial on the wafer, may be bonded together. The wafers may havedevices or integrated circuits formed therein. The devices and circuitsin the wafers bonded together may be interconnected. The wafers may havea non-planar surface or an irregular surface topology upon which amaterial is deposited to form the bonding surfaces.

[0018] Forming at least one of the bonding surfaces may includedepositing a polishable material on a non-planar surface. Depositingsaid polishable material may include depositing one of silicon oxide,silicon nitride or a dielectric polymer. The bonding surfaces may bepolished using a method such as chemical-mechanical polishing. Thesurfaces may also be etched prior to the polishing.

[0019] The etching step may also include activating the first and secondbonding surfaces and fonning selected bonding groups on the first andsecond bonding surfaces. Bonding groups may also be formed. capable offorming chemical bonds at approximately room temperature, and chemicalbonds may be formed between the bonding surfaces allowing bonded groupsto diffuse or dissociate away from an interface of the bonding surfaces.The chemical bonds can increase the bonding strength between the bondingsurfaces by diffusing or dissociating away said bonding groups.

[0020] After said etching step, the bonding surfaces may be immersed ina solution to form bonding surfaces terminated with desired species. Thespecies may comprise at least one of a silanol group, an NH₂ group, afluorine group and an HF group. Also, a monolayer of one of a desiredatom and a desired molecule may be formed on the bonding surface.Terminating the surface may include rinsing said bonding materials in anammonia-based solution after said slightly etching. The ammonia-basedsolution may be ammonium hydroxide or ammonium fluoride.

[0021] The method may also include exposing the bonding surfaces to oneof an oxygen, argon, NH₃ and CF₄ RIE plasma process. Silicon dioxide maybe deposited as to form the bonding surfaces, and etched using the RIEprocess.

[0022] The etching process may create a defective or damaged zoneproximate to the bonding surfaces. The defective or damaged zone canfacilitate the removal of bonding by-products through diffusion ordissociation.

[0023] The method may also include steps of forming first and secondbonding surfaces, etching the bonding surfaces, terminating the bondingsurfaces with a species allowing formation of chemical bonds at aboutroom temperature, and bonding the bonding surfaces at about roomtemperature, or may include steps of forming the bonding surfaces eachhaving a surface roughness in a range of 0.1 to 3 nm, removing materialfrom the bonding surfaces while maintaining said surface roughness, anddirectly bonding the bonding surfaces at room temperature with a bondingstrength of at least 500 mJ/m², at least 1000 mJ/m², or at least 2000mJ/m².

[0024] The objects of the invention may also be achieved by a bondeddevice having a first material having a first etched bonding surface,and a second material having a second etched bonding surface directlybonded to the first bonding surface at room temperature having a bondingstrength of at least 500 to 2000 mJ/m². The bonding surfaces may bebeing activated and terminated with a desired bonding species, and thedesired species may include a monolayer of one of a desired atom and adesired molecule on said bonding surface or at least one of a silanolgroup, an NH₂ group, a fluorine group and an HF group. The bondingsurfaces may each have a defective region located proximate to saidfirst and second bonding surfaces, respectively.

[0025] The first material may include a surface of a first semiconductorwafer having devices formed therein, and the second material may includea surface of a second semiconductor wafer having devices formed therein.Devices in the wafers may be interconnected, and the wafers may be ofdifferent technologies. The wafers may also have an integrated circuitformed therein, and devices or circuits in the wafers may beinterconnected.

[0026] One of said first and second wafers may be a device region afterremoving a substantial portion of a substrate of said one of said firstand second wafers. The wafers may have an irregular surface topology.

[0027] The first material may include a first wafer containingelectrical devices and having a first non-planar surface, and the firstbonding surface may include a polished and etched deposited oxide layeron said first non-planar surface. The second material may include asecond wafer containing electrical devices and having a secondnon-planar surface, and the second bonding surface may include apolished, planarized and slightly etched deposited oxide layer on thesecond non-planar surface.

[0028] The first material may include a first wafer containingelectrical devices and having a first surface with irregular topology,and the first bonding surface may include a polished, planarized andslightly etched deposited oxide layer on the first surface. The secondmaterial may include a second wafer containing electrical devices andhaving a second surface with irregular topology, and the second bondingsurface may include a polished, planarized and slightly etched depositedoxide layer on the second surface.

[0029] The bonded device according to the invention may also include afirst material having a first etched and activated bonding surfaceterminated with a first desired bonding species, and a second materialhaving a second etched and activated bonding surface terminated with asecond desired bonding species bonded to the first bonding surface atroom temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] A more complete appreciation of the invention and many of theattendant advantages thereof are readily obtained as the same becomebetter understood by reference to the following detailed descriptionwhen considered in connection with the accompanying drawings, wherein:

[0031]FIG. 1 is a flow chart of the method according to the invention;

[0032]FIG. 2 is a flow chart of an example of the method according tothe invention;

[0033] FIGS. 3A-3E are diagrams illustrating a first embodiment of amethod according to the invention;

[0034]FIG. 4 is a diagram illustrating bonding according to theinvention using silicon oxide;

[0035]FIG. 5 is a diagram illustrating bonding according to theinvention using silicon;

[0036]FIGS. 6A and 6B are graphs of room temperature bonding energyversus storage time;

[0037]FIG. 7 is a diagram of a bonding fixture used in the invention; nd

[0038]FIG. 8 is a fluorine concentration profile by SIMS (Secondary IonMass Spectroscopy) near the bonding interface of deposited oxide coveredsilicon wafers that were very slight etched by diluted HF beforebonding.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Referring to FIGS. 1 and 3A-3E, a first embodiment of the methodaccording to the invention will be described. Wafer 30, preferably aprocessed semiconductor device wafer and more preferably a processedsilicon device wafer, contains a device layer 31 with processed devices.Device layer 31 may contain a number of layers and include surfaceregions of wafer 30. The surface topography of layer 31 is typicallynonplanar. Layer 31 may also represent a processed integrated circuitcontaining any number of layers such as active devices, interconnection,insulation, etc.

[0040] The integrated circuit may be fully processed, or partiallyprocessed where the remaining processing is performed after the bondingprocess. The processing after the bonding may include full or partialsubstrate removal or via formation between the bonded wafers forinterconnection.

[0041] On layer 31 a bonding layer 32 is formed (step 1, FIG. 1).Bonding layer 32 may be any solid state material or mixed materialswhich can be deposited or formed at low temperatures and can be polishedto a sufficiently smooth surface. Layer 32 may be an insulator, such asSiO₂, silicon nitride, amorphous silicon formed using chemical vapordeposition (CVD) or plasma-enhanced CVD (PECVD), sputtering or byevaporation. Other materials such as polymers, semiconductors orsintered materials may also be used. Layer 32 should have thicknessgreater than the surface topography of layer 31.

[0042] The surface 33 of layer 32 is planarized and smoothed, as shownin step 2 of FIG. 1 and in FIG. 3B. It is noted that theroughness/planarity of surface 33 is exaggerated in FIG. 3A forillustrative purposes. This step may be accomplished usingchemical-mechanical polishing. Surface 33 is preferably polished to aroughness of about no more than about 3 nm and preferably no more thanabout 0.1 nm and be substantially planar. The surface roughness valuesare typically given as root-mean square (RMS) values. Also, the surfaceroughness may be given as mean values which are nearly the same as theRMS values. After polishing surface 33 is cleaned and dried to removeany residue from the polishing step. Polished surface 33 is preferablythen rinsed with a solution.

[0043] The bonding surface may also be etched prior to polishing toimprove the planarity and/or surface roughness. The etching can beeffective to remove high spots on the bonding surface by selectiveetching of the high spots using, for example, standard photolithographictechniques. For example, a layer of silicon nitride can be embeddedwithin a silicon dioxide bonding layer 32 that can serve as an etch stopwhen using a solution containing HF. The etch stop material may be usedto improve uniformity, reproducibility, and manufacturability.

[0044]FIG. 3B illustrates layer 32 having upper surface 34 after thepolishing/planarization and cleaning steps. Surface 34 then undergoes anactivation process (step 3, FIG. 1). This activation process is anetching process and preferably a very slight etch (VSE) process. Theterm VSE means that the root-mean-square micro-roughness (RMS) of thevery slightly etched surface remains at approximately the unetchedvalue, typically <0.5 nm and preferably in the range of 0.1 nm to 3 nm.The optimum amount of material removed depends upon the material and themethod used for removal. Typical amounts removed vary from Angstroms toa few nanometers. It is also possible to remove more material. VSE alsoincludes the breaking of bonds on the treated surfaces and can occurwithout significant removal of material. The VSE is distinct from simplemodification of the surface by, for example, charging the surface withelectronic charge or damaging the surface layer. In a first example ofthe method according to the invention, the VSE process consists of a gasor mixed gas (such as oxygen, argon, nitrogen, CF₄, NH₃) plasma processat a specified power level for a specified time (FIG. 3C). The power andduration of the plasma process will vary depending upon the materialsused to obtain the desired bond energy. Examples are given below, but ingeneral, the power and duration will be determined empirically.

[0045] The plasma process may be conducted in different modes. Bothreactive ion etch (RIE) and plasma modes may be used, as well as aninductively-coupled plasma mode (ICP). Sputtering may also be used. Dataand examples are given below in both the RIE and plasma modes.

[0046] The VSE process etches the surface very slightly via physicalsputtering and/or chemical reaction and preferably is controlled to notdegrade the surface roughness of the bonding surfaces. The surfaceroughness may even be improved depending upon the VSE and materialsetched. Almost any gas or gas mixture that will not etch surface 34excessively can be used for the room temperature bonding methodaccording to the invention.

[0047] The VSE serves to clean the surface and break bonds of the oxideon the wafer surface. The VSE process can thus enhance the surfaceactivation significantly. A desired bonding species can be used toterminated on surface 34 during the VSE by proper design of the VSE.Alternatively, a post-VSE treatment that activates and terminates thesurface with a desired terminating species during the post-VSE processmay be used.

[0048] The desired species further preferably forms a temporary bond tothe surface 34 atomic layer, effectively terminating the atomic layer,until a subsequent time that this surface can be brought together with asurface terminated by the same or another bonding species 36 as shown inFIG. 3D. Desired species on the surfaces will further preferably reactwith each other when they are in sufficiently close proximity allowingchemical bonding between surfaces 34 and 36 at low or room temperaturethat is enhanced by diffusion or dissociation and diffusion of thereacted desired species away from the bonding interface.

[0049] The post-VSE process preferably consists of immersion in asolution containing a selected chemical to generate surface reactionsthat result in terminating the bonding surface 34 with desired species.The immersion is preferably performed immediately after the VSE process.The post-VSE process may be performed in the same apparatus in which theVSE process is conducted. This is done most readily if both VSE andpost-VSE processes are either dry, i.e, plasma, RIE, ICP, sputtering,etc, or wet, i.e., solution immersion. A desired species preferablyconsists of a monolayer or a few monolayers of atoms or molecules.

[0050] The post-VSE process may also consist of a plasma, RIE, or otherdry process whereby appropriate gas chemistries are introduced to resultin termination of the surface with the desired species. The post-VSEprocess may also be a second VSE process. The termination process mayalso include a cleaning process where surface contaminants are removedwithout VSE. In this case, a post-cleaning process similar to thepost-VSE processes described above then results in a desired surfacetermination.

[0051] The post-VSE or post-cleaning process may or may not be needed totenminate surfaces with desired species if the activated surface bondsby the cleaning or VSE process are subsequently sufficiently weaklysurface reconstructed and can remain sufficiently clean before bondingsuch that subsequent bonding with a similar surface can form a chemicalbond.

[0052] The wafers are optionally rinsed then dried. Two wafers arebonded by aligning them (if necessary) and bringing them together tofonm a bonding interface. As shown in FIG. 3D, a second wafer 35 hasbeen processed in the manner shown in FIG. 3C to prepare bonding surface36. The two wafers are brought together by, for example, commerciallyavailable wafer bonding equipment (not shown) to initiate bondinginterface 37 (FIG. 3E).

[0053] A spontaneous bond then typically occurs at some location in thebonding interface and propagates across the wafer. As the initial bondbegins to propagate, a chemical reaction such as polymerization thatresults in chemical bonds takes place between species used to tenninatesurfaces 34 and 36 when the surfaces are in sufficient proximity. Thebonding energy is defined as the specific surface energy of one of theseparated surfaces at the bonding interface that is partially debondedby inserting a wedge. The by-products of the reaction then diffuse awayfrom. the bonding interface to the wafer edge or are absorbed by thewafers, typically in the surrounding materials. The by-products may alsobe converted to other by-products that diffuse away or are absorbed bythe wafers. The amount of covalent and/or ionic bonding may be increasedby removal of converted species resulting in further increase in bondstrength.

[0054] FIGS. 4A-4E show surface conditions and the bonding propagationto form covalent bonds in a the case of a planar Si wafer covered withsilicon oxide. On Si wafer 40 an SiO₂ layer 41 is formed, which has beenpolished and planarized. Surface 42 of layer 41 is subjected to the VSEprocess to produce an activated surface (FIG. 4A). On a second wafer 44a second SiO₂ layer 45 is formed, and surface 46 is subjected to a VSEprocess to activate surface 46 (FIG. 4B). Desired species are tenninatedon surface 46 and are shown as lines 43 in FIG. 4C. Either or both of aVSE and post-VSE processes are used to properly terminate surface 46.While not shown, surface 42 may also be terminated using a post-VSEprocess. Wafer 44 is brought together with wafer 40 (FIG. 4D) and bonds46 begin to form. the bonding propagates and by-products are removed(indicated as arrows 47) and chemical bonds (such as covalent) areformed, as shown in FIG. 4E.

[0055] The bonding immediately after the RIE process may use a specialbonding fixture allowing immediate in situ bonding of the etched wafers.A diagram of the fixture is shown in FIG. 7. In plasma chamber 75 aretwo wafers to be bonded 70 disposed on RF electrodes 76 and 77. A plasmais formed in zone 79 by the application of RF power to the electrodesvia moveable vacuum RF power feedtlirough 74 and by the introduction ofan appropriate gas or gas mixture through gas feedthrough 73. Element 71is a vacuum feedthrough for mechanical actuator (not shown) to retractretractable spacer 72. Chamber 75 is pumped down to a desired vacuumlevel via pumps (not shown) and chamber inlet 78. In the case where apost-VSE process or post cleaning process is also a dry process, asdiscussed above, the VSE and post-VSE or post-cleaning may be conductedin chamber 75.

[0056] After the plasma treatment to conduct the VSE process, themechanical spacers 72 are retracted by the mechanical actuator and thewafers 70 are moved into contact with to begin the bonding process. Thebonded wafers are then moved from the chamber into ambient or intoanother vacuum chamber (not shown) and stored for a desired period toallow the bonding to propagate by a wafer handling system (not shown).

[0057] The materials of the bonding layers preferably have an openstructure so that the by-products of the polymerization reaction can beeasily removed. The bonding species on the opposing bonding surfacesmust be able to react at room temperature to form a strong or chemicalbond. The bond energy is sufficiently high to virtually eliminateslippage between wafers after subsequent heat treatments associated witha subsequent processing or operation when wafers have different thermalexpansion coefficients. Lack of slippage is manifest by a lack of waferbowing upon inspection after the subsequent processing or operation.

[0058] In order to achieve the high bonding energies, it is preferablefor at least one of the wafers to be as thin as possible because a thinwafer allows compliance to accommodate a lack of perfect surfaceplanarization and smoothness. Thinning to thickness of about 10 mils to10 microns is effective.

[0059] The bonded wafers are preferably stored at ambient or at low orroom temperature after bonding to allow removal of species or convertedspecies for a specified period of time depending upon the materials andspecies used. Twenty four hours is usually preferable. The storage timeis dependent upon the type of plasma process used. Chemical bonds may beobtained more quickly, in a matter of minutes, when certain plasmaprocesses such as an Ar plasma are used. For example, 585 mJ/m² bondswere obtained in immediately after bonding and over 800 mJ/m2 wereobserved after 8 hours for deposited oxides etched by an Ar plasmafollowed by NH₄OH dip.

[0060] Annealing the bonded wafers during bonding may increase thebonding strength. The annealing temperature should be below 200° C. andmay be typically in the range of 75-100° C. Storing the bonded wafersunder vacuum may facilitate the removal of residual gasses from thebonding surfaces, but is not always necessary.

[0061] All of the processes above may be carried out at or near roomtemperature. The wafers are bonded with sufficient strength to allowsubsequent processing operations (lapping, polishing, substrate removal,chemical etching, lithography, masking, etc.). Bonding energies ofapproximately 500-2000 mJ/m² or more can be achieved (see FIG. 6A).

[0062] At this point (FIG. 3E) it is possible to remove a part or all ofthe substrate of wafer 35 by, for instance, lapping and etch back. Thelayer of devices of wafer 35 is thus transferred onto wafer 30. Thedevices from the two layers may be interconnected. Additional device orcircuit layers may be bonded and interconnected to form a multilayerstructure. Different types of wafers, devices or circuits may be bonded,as well as different technologies (i.e. CMOS and bipolar or III-V HBTand Si CMOS). Other elements or materials such as thermal spreaders,surrogate substrates, antennas, wiring layers, a pre-formed multi-layerinterconnects, etc. may be bonded to produce different types of circuitsor systems, as desired.

[0063] In an example, shown in FIG. 2, PECVD SiO₂ is deposited on a Siwafer containing devices. Surface 34, after the plasma (such as argon,oxygen or CF₄) treatment, is mainly terminated by Si—OH groups due tothe availability of moisture in the plasma system and in air. After theplasma treatment, the wafers are immediately immersed in solution suchas ammonium hydroxide (NH₄OH), NH₄F or HF for a period such as between10 and 120 seconds. After immersing the wafers in the NH₄OH solution,many Si—OH groups are replaced by Si—NH2 groups according to thefollowing substitution reaction:

2Si—OH+2NH4OH→2Si—NH2+4HOH   (1)

[0064] Alternatively, many Si—F groups are terminating on the PECVD SiO₂surface after an NH₄F or HF immersion.

[0065] The hydrogen bonded Si—NH2:Si—OH groups or Si—NH2:Si—NH2 groupsacross the bonding surfaces can polymerize at room temperature informing Si—O—Si or Si—N—N—Si (or Si—N—Si) covalent bonds:

Si—NH2+Si—OH→Si—O—Si+NH3   (2)

Si—NH2+Si—NH2→Si—N—N—Si+2H2   (3)

[0066] Alternatively, the HF or NH₄F dipped oxide surfaces areterminated by Si—F groups in addition to Si—OH groups. Since HF or NH₄Fsolution etches silicon oxide strongly, their concentrations must becontrolled to an adequately low level, and the immersion time must besufficiently short. This is an example of a post-VSE process being asecond VSE process. The covalent bonds across the bonding interface areformed due to the polymerization reaction between hydrogen bonded Si—HFor Si—OH groups:

Si—HF+Si—HF→Si—F—F—Si+H2   (4)

Si—F+Si—OH→Si—O—Si+HF   (5)

[0067]FIG. 8 shows the fluorine concentration profile of bonded thermaloxide covered silicon wafers that were dipped in 0.05% HF before roomtemperature bonding. A fluorine concentration peak is clearly seen atthe bonding interface. This provides evidence of the chemical processdescribed above where the desired species are located at the bondinginterface.

[0068] Since reaction (2) is reversible only at relatively hightemperatures of ˜500° C., the formed siloxane bonds should not beattacked by NH₃ at lower temperatures. It is known that H₂ molecules aresmall and diffuse about 50 times quicker than water molecules in oxide.The existence of a damaged layer near the surface of an adequatethickness i.e. a few nm, will facilitate the diffusion or dissolution ofNH₃, and HF and hydrogen in reactions (2), (3), (4) and/or (5) in thislayer and enhancement of the chemical bond. The three reactions resultin a higher bonding energy of SiO₂/SiO₂ bonded pairs at room temperatureafter a period of storage time to allow NH₃ or H₂ to diffuse away.

[0069] In the example of FIG. 2, the plasma treatment may create adamaged or defective area in the oxide layer near the bonding surface.The zone extends for a few monolayers. The damaged or defective areaaids in the removal of bonding by-products. Efficient removal of thebonding by-products improves the bonding strength since the by-productscan interfere with the bonding process by preventing high-strength bondfrom forming.

[0070] Many different surfaces of materials may be smoothed and/orplanarized, followed by a cleaning process, to prepare for bondingaccording to the invention. These materials can be room temperaturebonded by mating surfaces with sufficient planarity, surface smoothness,and passivation that includes cleaning, and/or VSE, activation andtermination. Amorphous and sintered materials, non-planar integratedcircuits, and silicon wafers are examples of such materials. Singlecrystalline semiconductor or insulating surfaces, such as SiO₂ or Sisurfaces, can also be provided with the desired surface roughness,planarity and cleanliness. Keeping the surfaces in high or ultra-highvacuum simplifies obtaining surfaces sufficiently free of contaminationand atomic reconstruction to achieve the strong bonding according to theinvention. Other semiconductor or insulator materials such as InP, GaAs,SiC, sapphire, etc., may also be used. Also, since PECVD SiO₂ may bedeposited on many types of materials at low temperatures, many differentcombinations of materials may be bonded according to the invention atroom temperature. Other materials may also be deposited as long asappropriate processes and chemical reactions are available for the VSE,surface activation, and termination.

[0071] For example, the method may also be used with silicon nitride asthe bonding material. Silicon nitride may be bonded to silicon nitride,or to silicon dioxide and silicon. Silicon oxide may also be bonded tosilicon. Other types of dielectric materials may be bonded togetherincluding aluminum nitride and diamond-like carbon.

[0072] The method may be applied to planar wafers having no devices orcircuits and one wafer with devices and circuits. The planar wafer maybe coated with a bonding layer, such as PECVD oxide or amorphoussilicon, and then processed as described above to bond the two wafers.The planar wafer may not need to be coated with a bonding layer if ithas sufficient smoothness and planarity and the proper bonding material.

[0073] As can be appreciated, the bonding process may be repeated withany number of wafers, materials or functional elements. For example, twodevice or IC wafers may be joined, followed by removing one of theexposed substrates to transfer a layer or more of devices, or just theactive regions of an IC.

[0074] The bonding according to the invention may be applied to joiningdifferent types of materials. For example, a silicon wafer can be bondedto another silicon wafer, or bond to an oxidized silicon wafer. The baresilicon wafer and the oxide covered wafer are immersed in HF, NH₄Fand/or NH₄OH and bonded after drying. The time for the immersion shouldbe less than about twenty minutes for the silicon wafer covered with thethin oxide since the NE₄OH solution etches silicon oxide. Since HF andNH₄F etches oxides strongly, very diluted solutions, preferably in0.01-0.2% range should be used for dipping of the silicon wafers.

[0075] After drying the silicon wafer and the oxide-covered wafer arebonded in ambient at room temperature. Reactions (2), (3), (4) and/or(5) take place at the bonding interface between the two wafers. Theplasma-treated wafers may also be immersed in deionized water instead ofthe NH₄OH solution.

[0076] The silicon bonding may be conducted with a bare silicon wafer,i.e. having a native oxide or a silicon wafer having an oxide layerformed on its surface as described above. During the oxygen plasmatreatment, the native oxide which if formed on the bare silicon wafer issputter etched, and the oxide layer formed on the silicon surface isetched. The final surface is an activated (native or formed) oxide. Whenrinsed in deionized water, the activated oxide surface is mainlyterminated with Si—OH groups. Since oxide growth in oxygen plasma hasbeen found to have less water than in normal native oxide layers, thewater from the original bonding bridge and generated by the followingpolymerization reaction (6) can be absorbed into the plasma oxidereadily.

Si—OH+Si—OH→Si—O—Si+H2O   (6)

[0077] FIGS. 5A-5E illustrate bonding two silicon wafers. Wafers 50 and52 have respective surfaces 51 and 53 with native oxides (not shown)subjected to a VSE process. Surface 53 is in FIG. 5C is shown terminatedwith a desired species 54. The two wafers are brought together and bonds55 begin to form (FIG. 5D). The bonding propagates and bondingby-products, in this case H₂ gas, are removed. The by-products beingremoved are shown as arrows 56 in FIG. 5E.

[0078] In addition to removal of the water from the bonding interface bydissolving into the plasma activated oxide of the oxidized siliconwafer, the water can also diffuse through the thin oxide layer on thebare silicon wafer to react with silicon. As the silicon surfaceunderneath the oxide has a damaged or defective zone, extending for afew monolayers, the water molecules that diffuse through the oxide layerand reach the damaged or defective zone can be converted to hydrogen atroom temperature and be removed readily:

Si+2H₂O→SiO₂+2H₂   (7)

[0079] The reverse reaction of (6) is thus avoided and the roomtemperature bonding energy increases enormously due to the formation ofcovalent Si—O—Si bonds.

[0080] If a relatively thick (˜5 run) oxide layer is formed, it willtake a long period of time for the water molecules to diffuse throughthis thick layer. On the other hand, if after the plasma treatment athin oxide layer is left or a too narrow defective zone is formed, waterthat can reach the silicon surface may not react sufficiently with thesilicon and convert to hydrogen. In both cases the bonding energyenhancement will be limited. The preferred oxygen plasma treatment thusleaves a minimum plasma oxide thickness (e.g., about 0.1-1.0 nm) and areasonably thick defective zone (e.g., about 0.1-0.3 nm) on the siliconsurface.

[0081] In a second embodiment, the VSE process uses wet chemicals. Forexample, an InP wafer having a deposited silicon oxide layer, as in thefirst embodiment, and a device layer are bonded to a AIN substratehaving a deposited oxide layer. After smoothing and planarizing the InPwafer bonding surface and the AIN wafer bonding surface, both wafers arecleaned in an standard RCA cleaning solution. The wafers are veryslightly etched using a dilute HF aqueous solution with an HFconcentration preferably in the range of 0.01 to 0.2%. About a fewtenths of a run is removed and the surface smoothness is not degraded asdetermined by AFM (atomic force microscope) measurements. Withoutdeionized water rinse, the wafers are spin dried and bonded in ambientair at room temperature. The resulting bonding energy has been measuredto reach ˜700 mJ/m² after storage in air. After annealing this bondedpair at 75° C. the bonding energy of 1500 mJ/m² was obtained., Thebonding energy has been measured to reach silicon bulk fracture energy(about 2500 mJ/m²) after annealing at 100° C. If the wafers are rinsedwith deionized water after the HF dip, the bonding energy at 100° C. isreduced to 200 mJ/m²,that is about one tenth of that obtained withoutthe rinse. This illustrates the preference of F to OH as a terminatingspecies.

[0082] In a third embodiment the VSE process consists of 0.1% HF etchingfollowed by 5 min dip in 0.02% HN₄F solution of thermally oxidizedsilicon wafers at room temperature after a standard cleaning process.Without rinsing in deionized water, the wafers are bonded after spindrying at room temperature. The bonding energy of the bonded pairsreaches ˜1700 mJ/m² after 100° C. annealing. If the wafers are rinsed inde-ionized water after the HF etching before bonding, the bonding energyof bonded pairs is only 400 mJ/m², again illustrating the preference ofF to OH as a terminating species.

[0083] Dilute NH₄F is used in the VSE process to etch silicon oxidecovered wafers in a fourth embodiment. The concentration of the NH₄Fshould be below 0.02% to obtain the desired bonding. The bonding energyof 600 mJ/m² can be achieved at room temperature after storage.

[0084] A fifth embodiment of the invention is used to bond Si surfaceshaving a native oxide of about 1 nm in thickness. In the fifthembodiment, after cleaning the Si surface by a standard RCA1 cleaningprocess, a VSE process using 5 min etching in 70% HNO₃+diluted HF(preferably 0.01 to 0.02%) is performed. Wafers are pulled out of thesolution vertically with a basically hydrophobic surface. Withoutrinsing in water, the wafers were bonded at room temperature in air. Inthis process covalent bonding occurs at room temperature with measuredbonding energies typically about 600 mJ/m². This bonding energy issignificantly increased to 1300 mJ/m² after annealing at 75° C. andreaches the fracture energy of bulk silicon (about 2500 mJ/m²) at atemperature of 100° C.

[0085] Instead of 70% HNO₃, diluted HNO₃ with water can be used in thesolution to achieve similar results. According to AMF measurements andhigh resolution transmission electron microscopy measurement results,the silicon is etched in the dilute HNO₃ VSE process at a rate of0.1-0.15 nm/min and a new thick oxide 2.5-3.5 nm in thickness is formed.

[0086] As further embodiments, the VSE process may consist of a dry etchthat has chemical and/or physical components. For a bare Si surface,chemical etching may result from SF₄/H₂ gas mixture while physicaletching may result from Ar etch. For a silicon oxide surface, chemicaletching may use CF₄ while physical etching may use oxygen or argon gas.It is also possible to use a thermally stable polymer material for thebonding materials and bond two polymer surfaces together. Examples arepolyimides or spin-on materials.

[0087] The mechanisms governing the increased bond energy at low or roomtemperature are similar. A very slight etching (VSE) of the bondingwafers by plasma to clean and activate the surfaces, and improve removalof by-products of interface polymerization to prevent the undesirablereverse reaction and rinse in appropriate solution to terminate thesurface with desired species to facilitate room temperature covalentbonding. The oxide covered wafer bonding case is similar except that adifferent surface termination is preferred. In bare silicon waferbonding, the highly reactive surface layers of oxide and silicon toallow water adsorption and conversion to hydrogen should be formed. Thehighly reactive layers can be a plasma thin oxide layer and a damagedsilicon surface layer. The oxide on the silicon wafer will also havesome damage. Not only O₂ plasma but also plasma of other gases (such asAr, CF₄) are adequate. Because during and after VSE the silicon surfaceis readily to react with moisture to form an oxide layer, and theunderlying damaged silicon layer is created by VSE. Since the VSE andby-products removal methods are rather general in nature, this approachcan be implemented by many means and apply to many materials.

EXAMPLE 1

[0088] In a first example, three inch <100>, 1-10 ohm-cm, boron dopedsilicon wafers were used. PECVD oxide was deposited on some of thesilicon wafers. For comparison, thermal oxidized silicon wafers werealso studied. The PECVD oxide thickness was 0.5 μm and 0.3 μm on thefront side and the back side of the wafers, respectively. Oxide isdeposited on both sides of the wafer to minimize wafer bow duringpolishing and improve planarization. A soft polish was performed toremove about 30 nm of the oxide and to smooth the front oxide surfaceoriginally having a root mean square of the micro-roughness (RMS) of˜0.56 nm to a final ˜0.18 nm. A modified RCA1 solution was used to cleanthe wafer surfaces followed by spin-drying.

[0089] Two wafers were loaded into the plasma system, both wafers areplaced on the RF electrode and treated in plasma in RIE mode. Forcomparison, some wafers were treated in plasma mode in which the waferswere put on the grounded electrode. An oxygen plasma was used with anominal flow rate of 16 scc/m. The RF power was 20-400 W (typically 80W) at 13.56 MHz and the vacuum level was 100 mTorr. The oxide coveredwafers were treated in plasma for times between 15 seconds to 5 minutes.The plasma treated silicon wafers were then dipped in an appropriatesolution or rinse with de-ionized water followed by spin-drying and roomtemperature bonding in air. Some of the plasma treated wafers were alsodirectly bonded in air without rinse or dipping.

[0090] The bonding energy was measured by inserting a wedge into theinterface to measure the crack length according to the equation:$\gamma = \frac{3t_{b}^{2}E_{1}t_{w1}^{3}E_{2}t_{tw2}^{3}}{16{L^{4}\left( {{E_{1}t_{w1}^{3}} + {E_{2}t_{w2}^{3}}} \right)}}$

[0091] E and tw are the Young's modulus and thickness for wafers one andtwo and tb is the thickness of a wedge inserted between the two wafersthat results in a wafer separation of length L from the edge of thewafers.

[0092] The room temperature bonding energy as a function of storage timeof bonded plasma treated oxide covered silicon wafers is shown in FIG.6A. This figure shows measured room temperature bonding energy versusstorage time for 4 different cases as shown. The results can besummarized as follows: (1) for dipped and bonded RIE plasma treatedoxide wafers, the room temperature bonding energy increases with storagetime and reaches a stable value after ˜20 h in air or at low vacuum; (2)RIE mode results in higher bonding energies than plasma mode; (3) tooshort a plasma exposure time or too low a plasma power provides a smallor negligible increase in bond energy; (4) NH₄OH dip after plasmatreatment shows a much higher increase in bonding energy than waterrinse; (5) direct bonding in air after plasma treatment without dippingor rinse shows an almost constant bonding energy with time. The bondingenergy of the directly bonded wafer pairs immediately after roomtemperature bonding is slightly higher than the de-ionized water rinsedor NH₄OH dipped wafer pairs.

[0093]FIG. 6B shows room temperature bonding of Si and AIN wafers withPECVD oxide deposited layers. After about 100 h of storage time abonding energy of over 2000 mJ/m² were observed.

[0094] Comparing different bonding materials, the bonding energy as afunction of storage time of O₂ plasma treated thermally oxidized siliconwafer pairs is similar to wafers with PECVD oxide, although the valuesof the room temperature bonding energy are somewhat lower.

[0095] After ˜24 h storage in air at room temperature, the bondingenergy as high as ˜1000 mJ/m2 was reached in the RIE mode plasma treatedand NH₄OH dipped PECVD oxide covered wafer pairs. Since the maximumbonding energy of a van der Waals bonded silicon oxide covered waferpairs is about 200 mJ/m2, a large portion of the bonding energy isattributed to the formation of covalent bonds at the bonding interfaceat room temperature according to the above equation.

EXAMPLES 2-3

[0096] The above process was applied to bond processed InP wafers (600μm thick) to AIN wafers (380 μm thick), or to bond processed Si (380 μmthick) and InP (600 μm thick) wafers, as second and third examples. Theprocessed InP device wafers are covered with PECVD oxide and planarizedand smoothed by chemical-mechanical polishing CMP. A PECVD oxide layeris also deposited on the AIN wafers and is planarized and smoothed toimprove the RMS surface roughness. The processed Si and processed InPwafers are deposited with PECVD oxide and planarized and smoothed usingCMP. After VSE similar to the example 1 bonding at room temperature, thebonded wafers are left in ambient air at room temperature.

[0097] After 24 hours storage at room temperature, bonding energy of1000 mJ/m2 and 1100 mJ/m2 were achieved for the InP/Si and InP/AINbonded pairs, respectively. For processed Si (380 μm thick) /oxidecovered AIN (280 μm thick) wafer pairs, the bonding energy at roomtemperature as high as 2500 mJ/m2 has been achieved. These roomtemperature bonded plasma treated wafer pairs have sufficient bondingstrength to sustain subsequent substrate lapping and etching and othertypical semiconductor fabrication processes before or after substrateremoval.

[0098] The InP substrate in the room temperature bonded InP/AIN pairswas lapped with 1900# Al2O3 powder from initial 600 μm thick to ˜50 μmthick followed by etching in an HCl/H3PO4 solutionto leave about a 2.0μm thick InP device layer on the AlN or Si wafer. The water and etchingsolution did not penetrate into the bonding interface.

[0099] Surfaces are sputter etched by energetic particles such asradicals, ions, photons and electrons in the plasma or RIE mode. Forexample, the O₂ plasma under conditions that bring about the desired VSEis sputter-etching about 2 Å/min of PECVD oxide as measured by areflectance spectrometry. For thermal oxide the sputter etching rate isabout 0.5 Å/min. The thickness of oxide before and after plasmatreatment was measured by a reflectance spectrometry and averaged from98 measured points on each wafer. The etching by O₂ plasma has not onlycleaned the surface by oxidation and sputtering but also broken bonds ofthe oxide on the wafer surfaces.

[0100] However, the surface roughness of plasma treated oxide surfacesmust not be degraded by the etching process. AFM measurements show thatcompared with the initial surface roughness, the RMS of the O₂ plasmatreated oxide wafers was ˜2 Å and did not change noticeably. On theother hand, if the etching is not sufficiently strong, the bondingenergy enhancement effect is also small. Keeping other conditionsunchanged when the O₂ plasma treatment was performed with plasma moderather than RIE mode, the etching of oxide surfaces is negligible andthe oxide thickness does not change. The final room temperature bondingenergy is only 385 mJ/m2 compared to 1000 mJ/m2 of RIE treated wafers(see FIG. 6A).

[0101] Other gas plasma has shown a similar effect. CF₄/O₂ RIE was usedto remove ˜4 nm of PECVD oxide from the wafer surfaces prior to bonding.The bonding energy of room temperature bonded PECVD oxide coveredsilicon wafers was also enhanced significantly in this manner andexceeds 1000 mJ/m2 after sufficient storage time (see also FIG. 6A).

[0102] An argon plasma has also been used for the VSE with a nominalflow rate of 16 scc/m. The RF power was typically 60 W at 13.56 MHz andthe vacuum level was 100 mtorr. The oxide covered silicon wafers weretreated in plasma in RIE mode for times between 30 seconds to 2 minutes.The plasma treated silicon wafers were then dipped in an NH₄OH solutionfollowed by spin-drying and room temperature bonding in air. The bondingenergy reached 800 mJ/m² at room temperature after only 8 h storage inair.

[0103] Obviously, numerous modifications and variations of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims, theinvention may be practiced otherwise than as specifically describedherein.

What is claimed as new and desired to be protected by Letters Patentsis:
 1. A bonding method, comprising: forming first and second bondingsurfaces; etching said first and second bonding surfaces; and bondingtogether at room temperature said first and second bonding surfacesafter said etching step.
 2. A method as recited in claim 1, wherein saidetching step comprises: etching said first and second bonding surfacessuch that respective surface roughnesses of said first and secondbonding surfaces after said etching are substantially the same asrespective surface roughnesses before said etching.
 3. A method asrecited in claim 2, comprising: forming said first and second bondingsurfaces to have a surface roughness in a range of 0.1 to 3.0 nm.
 4. Amethod as recited in claim 1, wherein said etching step comprises:activating said first and second bonding surfaces and forming selectedbonding groups on said first and second bonding surfaces.
 5. A method asrecited in claim 4, comprising: forming bonding groups capable offorming chemical bonds at approximately room temperature.
 6. A method asrecited in claim 1, comprising: forming chemical bonds between saidbonding surfaces allowing bonded groups to diffuse or dissociate awayfrom an interface of said first and second bonding surfaces.
 7. A methodas recited in claim 6, comprising: increasing bonding strength betweensaid first and second bonding surfaces by diffusing or dissociating awaysaid bonding groups.
 8. A method as recited in claim 1, wherein saidetching step comprises: forming a monolayer of one of a desired atom anda desired molecule on said bonding surface.
 9. A method as recited inclaim 8, wherein said etching step comprises: forming a few monolayersof one of a desired atom and a desired molecule on said bonding surface.10. A method as recited in claim 1, comprising: after said etching step,immersing said first and second bonding surfaces in a solution to formbonding surfaces terminated with desired species.
 11. A method asrecited in claim 10, wherein said species comprise at least one of asilanol group, an NH₂ group, a fluorine group and an HF group.
 12. Amethod as recited in claim 10, wherein said etching step comprises:forming a monolayer of one of a desired atom and a desired molecule onsaid bonding surface.
 13. A method as recited in claim 1, wherein saidetching comprises: exposing said first and second bonding surfaces to aplasma.
 14. A method as recited in claim 1, comprising: exposing saidfirst and second bonding surfaces to one of an oxygen, argon, NH₃ andCF₄ plasma process.
 15. A method as recited in claim 14, comprising:conducting said plasma process in one of RIE mode, ICP mode, plasma modeand sputtering mode.
 16. A method as recited in claim 1, comprising:polishing respective first and second bonding surfaces to respectivedesired surface roughnesses and planarity; and etching said first andsecond bonding surfaces after said polishing to activate said first andsecond bonding surfaces.
 17. A method as recited in claim 16, wherein:forming at least one of said first and second bonding surfaces comprisesdepositing a polishable material on a non-planar surface.
 18. A methodas recited in claim 17, wherein depositing said polishable materialcomprises depositing one of silicon oxide, silicon nitride or adielectric polymer.
 19. A method as recited in claim 1, wherein saidetching step comprises: increasing available bonding energy of bondingpairs on said first and second bonding surfaces at approximately roomtemperature.
 20. A method as recited in claim 19, comprising: obtaininga bond of at least 500 mJ/m².
 21. A method as recited in claim 19,comprising: obtaining a bond of at least 1000 mJ/m².
 22. A method asrecited in claim 19, comprising: obtaining a bond of at least 2000mJ/m².
 23. A method as recited in claim 1, comprising: forming a bond ofat least 500 mJ/m².
 24. A method as recited in claim 1, comprising:obtaining a bond of at least 1000 mJ/m².
 25. A method as recited inclaim 1, comprising: obtaining a bond of at least 2000 mJ/m².
 26. Amethod as recited in claim 1, comprising: forming chemical bonds betweensaid bonding surfaces.
 27. A method as recited in claim 26, comprising:forming chemical bonds between said bonding surfaces in one of ambientand vacuum.
 28. A method as recited in claim 26, comprising: formingchemical bonds between said bonding surfaces in one of low and ultrahigh and vacuum.
 29. A method as recited in claim 1, comprising: forminga bond of sufficient energy to virtually eliminate wafer bowing duringsubsequent processing of said bonded bonding surfaces.
 30. A method asrecited in claim 29, comprising: forming a bond of sufficient energy tovirtually eliminate wafer bowing during subsequent thermal cycling ofsaid bonded bonding surfaces.
 31. A method as recited in claim 1,wherein said etching step comprises: increasing available bonding energyof bonding pairs on said first and second bonding surfaces atapproximately room temperature; and propagating said bonding at roomtemperature.
 32. A method as recited in claim 31, comprising:propagating chemical bonding at room temperature.
 33. A method asrecited in claim 1, comprising: depositing silicon dioxide as first andsecond bonding materials having said first and second bonding surfaces;and etching said first and second bonding surfaces using an oxygenplasma.
 34. A method as recited in claim 33, comprising: rinsing saidbonding materials in an ammonia-based solution after said etching.
 35. Amethod as recited in claim 34, comprising: rinsing said bondingmaterials in ammonium hydroxide after said etching.
 36. A method asrecited in claim 34, comprising: rinsing said bonding materials inammonium fluoride after said etching.
 37. A method as recited in claim1, comprising: etching said first and second bonding surfaces undervacuum; and bonding said first and second bonding surfaces withoutbreaking said vacuum.
 38. A method as recited in claim 1, comprising:depositing a bonding material on each of first and second surfaces toobtain said first and second bonding surfaces.
 39. A method as recitedin claim 38, comprising: depositing one of silicon dioxide and siliconnitride as said bonding material.
 40. A method as recited in claim 1,comprising: depositing silicon dioxide as said bonding material; etchingsaid silicon dioxide using one of oxygen, CF₄, and Ar plasma RIE; andrinsing said silicon dioxide in an ammonia-based solution after saidetching.
 41. A method as recited in claim 1, comprising: etching saidfirst and second bonding materials using a wet etch process.
 42. Amethod as recited in claim 42, comprising: immersing said first andsecond bonding surfaces into a solution after said etching.
 43. A methodas recited in claim 1, comprising: depositing silicon dioxide as saidbonding material; etching said silicon dioxide using one of diluted HFand diluted NH₄F.
 44. A method as recited in claim 43, comprising:rinsing said silicon dioxide in an ammonia-based solution after saidetching.
 45. A method as recited in claim 1, comprising: forming saidfirst and second bonding surfaces as silicon; and etching said bondingsurfaces using a solution of HNO₃ and diluted HF.
 46. A method asrecited in claim 1, comprising: forming said first and second bondingsurfaces as silicon each having a native oxide layer; and activatingsaid native oxide layer using said etching step.
 47. A method as recitedin claim 1, comprising: forming said first and second bonding surfaceseach as silicon having a native oxide layer; and exposing said first andsecond bonding surfaces to an oxygen plasma to etch said native oxidelayers.
 48. A method as recited in claim 47, creating a defective zonein said silicon during plasma etching.
 49. A method as recited in claim1, comprising: etching said first and second bonding materials using aplasma RIE process; forming a region having defects proximate to saidbonding surface; and removing bonding by-products using said region. 50.A method as recited in claim 1, wherein said etching comprises:activating said first and second bonding surfaces; and creating a regionunder said first and second bonding surfaces for removing bondingby-products.
 51. A method as recited in claim 1, comprising: creating aregion proximate to said first and second bonding surfaces for at leastone of removal and conversion of bonding by-products to a speciescapable of being absorbed by or diffusing away from said bondingsurfaces.
 52. A method as recited in claim 1, comprising: forming saidfirst bonding surface by depositing an oxide layer on a firstsemiconductor wafer; forming said second bonding surface by depositingan oxide layer on a second semiconductor wafer; and bonding said firstand second semiconductor wafers.
 53. A method as recited in claim 1,comprising: forming said first bonding surface as a deposited oxidelayer on a first semiconductor wafer, said first wafer comprising afirst substrate and a first active region; forming said second bondingsurface as a deposited oxide layer on a second semiconductor wafer, saidsecond wafer comprising a second substrate and a second active region;bonding said first and second semiconductor wafers; and removing atleast a substantial portion of one of said first and second substratesafter said bonding.
 54. A method as recited in claim 1, comprising:forming said first bonding surface as a deposited oxide layer on asemiconductor wafer, said wafer comprising a substrate and an activeregion; forming said second bonding surface as a surrogate substrate;bonding said wafer and said surrogate substrate; and removing at least asubstantial portion of said first substrate after said bonding.
 55. Amethod as recited in claim 1, wherein said bonding comprises:maintaining contact between said first and second bonding surfaces for aspecified period to produce bonding polymerization and allow removal ofby-products.
 56. A method as recited in claim 55, comprising:maintaining said contact between said first and second bonding surfacesfor a period less than about 20 hours.
 57. A method as recited in claim1, wherein said bonding comprises: maintaining said first and secondbonding surfaces for a specified period in ambient to remove bondingby-products.
 58. A method as recited in claim 1, comprising: etchingsaid first and second bonding surfaces using a bonding fixture undervacuum; bonding said first and second bonding surfaces using saidfixture to bring together said first and second bonding surfaces whilemaintaining said vacuum.
 59. A method as recited in claim 1, comprising:forming a first oxide layer on a first wafer containing electricaldevices; and polishing said first oxide layer to form said first bondingsurface.
 60. A method as recited in claim 59, comprising: forming asecond oxide layer on a second wafer containing electrical devices; andpolishing said second oxide layer to form said second bonding surface.61. A method as recited in claim 60, comprising: forming said firstoxide layer on said first wafer containing electrical devices of a firsttechnology; and forming said second oxide layer on said second wafercontaining electrical devices of a second technology different from saidfirst technology.
 62. A method as recited in claim 60, comprising:interconnecting said first and second devices.
 63. A method as recitedin claim 60, comprising: forming said first bonding surface on a surfaceof a one of a thermal spreader, surrogate substrate, antenna, wiringlayer, and pre-formed multi-layer interconnect.
 64. A method as recitedin claim 60, comprising: forming said second bonding surface on asurface of a one of a thermal spreader, surrogate substrate, antenna,wiring layer, and pre-formed multi-layer interconnect.
 65. A method asrecited in claim 1, comprising: forming said first bonding surface on afirst wafer containing a first integrated circuit.
 66. A method asrecited in claim 65, comprising: forming said second bonding surface ona second wafer containing a second integrated circuit.
 67. A method asrecited in claim 66, comprising: forming said first bonding surface onsaid first wafer containing said first integrated circuit of a firsttechnology; and forming said second bonding surface on said second wafercontaining said second integrated circuit of a second technologydifferent from said first technology.
 68. A method as recited in claim66, comprising: interconnecting said first and second integratedcircuits.
 69. A method as recited in claim 1, comprising: said first andsecond bonding surfaces being substantially planar.
 70. A method asrecited in claim 1, wherein: forming said first and second bondingsurfaces comprises depositing a dielectric material.
 71. A method asrecited in claim 70, comprising: polishing said dielectric material to adesired planarity and surface roughness.
 72. A method as recited inclaim 70, comprising: depositing said dielectric material on anon-planar surface.
 73. A method as recited in claim 72, wherein: saidpolishing comprises chemical-mechanical polishing.
 74. A method asrecited in claim 1, comprising: forming said first and second bondingsurfaces to be non-planar; and polishing said first and second bondingsurfaces to a desired planarity and surface roughness
 75. A method asrecited in claim 74, wherein: said polishing compriseschemical-mechanical polishing.
 76. A method as recited in claim 1, wheresaid etching comprises: activating said bonding surfaces; andterminating said bonding surfaces with a desired species.
 77. A methodas recited in claim 1, wherein said etching comprises: a first etchingstep to activate said bonding surfaces; and a second etching step toterminate said bonding surfaces with a desired species.
 78. A method asrecited in claim 1, comprising: obtaining etched bonding surfaces usingsaid etching step; and exposing said bonding surfaces to a gaseouschemical environment to terminate said etched bonding surfaces with adesired species.
 79. A method as recited in claim 1, comprising: forminga first oxide layer on a first wafer containing electrical devices andhaving a non-planar surface; and forming a second oxide layer on asecond wafer containing electrical devices; and polishing said first andsecond oxide layers to form said first and second bonding surfaces,respectively.
 80. A method as recited in claim 79, comprising: formingsaid second oxide layer on said second wafer having a non-planarsurface.
 81. A method as recited in claim 1, comprising: forming a firstoxide layer on a first wafer containing electrical devices and having anirregular surface topology; and forming a second oxide layer on a secondwafer containing electrical devices; and polishing said first and secondoxide layers to form said first and second bonding surfaces,respectively.
 82. A method as recited in claim 81, comprising: formingsaid second oxide layer on said second wafer having an irregular surfacetopology.
 83. A bonding method, comprising: forming first and secondbonding surfaces each having a surface roughness in a range of 0.1 to 3nm; removing material from said first and second bonding surfaces whilemaintaining said surface roughness; and directly bonding said first andsecond bonding surfaces at room temperature with a bonding strength ofat least 500 mJ/m².
 84. A method as recited in claim 83, comprising:directly bonding said first and second bonding surfaces at roomtemperature with a bonding strength of at least 1000 mJ/m².
 85. A methodas recited in claim 83, comprising: directly bonding said first andsecond bonding surfaces at room temperature with a bonding strength ofat least 2000 mJ/m².
 86. A method as recited in claim 83, comprising:activating said first and second bonding surfaces and forming selectedbonding groups on said first and second bonding surfaces.
 87. A methodas recited in claim 83, comprising: polishing respective first andsecond bonding surfaces to said surface roughness; and etching saidfirst and second bonding surfaces after said polishing to activate saidfirst and second bonding surfaces.
 88. A method as recited in claim 83,comprising: converting bonding by-products to a species capable of beingabsorbed by or diffusing away from said bonding surfaces during saidbonding step.
 89. A method as recited in claim 83, comprising: etchingsaid first and second bonding surfaces using a plasma RIE process;forming a subsurface layer having defects; and removing bondingby-products using said subsurface layer.
 90. A method as recited inclaim 83, comprising: forming said first bonding surface as a surface ofa first semiconductor wafer having devices formed therein; and formingsaid second bonding surface as a surface of a second semiconductor waferhaving devices formed therein.
 91. A method as recited in claim 90,wherein one of said first and second wafers comprises a substrate, saidmethod comprising: removing a substantial portion of said one of saidfirst and second wafers.
 92. A method as recited in claim 90,comprising: interconnecting devices in said first and second wafers. 93.A method as recited in claim 83, comprising: forming a first insulatinglayer on a first wafer containing electrical devices; polishing saidfirst insulating layer to form said first bonding surface; forming asecond insulating layer on a second wafer containing electrical devices;and polishing said second oxide layer to form said second bondingsurface.
 94. A method as recited in claim 83, comprising: forming afirst insulating layer on a first wafer containing electrical devicesand having an irregular surface topology; polishing said firstinsulating layer to form said first bonding surface; forming a secondinsulating layer on a second wafer containing electrical devices andhaving an irregular surface topology; and polishing said second oxidelayer to form said second bonding surface.
 95. A bonding method,comprising: forming first and second bonding surfaces; etching saidfirst and second bonding surfaces; terminating said first and secondbonding surfaces with a species allowing formation of chemical bonds atabout room temperature; and bonding said first and second bondingsurfaces at about room temperature.
 96. A method as recited in claim 95,comprising: bonding said first and second bonding surfaces at roomtemperature with a bonding strength of at least 500 mJ/m².
 97. A methodas recited in claim 95, comprising: bonding said first and secondbonding surfaces at room temperature with a bonding strength of at least1000 mJ/m².
 98. A method as recited in claim 95, comprising: bondingsaid first and second bonding surfaces at room temperature with abonding strength of at least 2000 mJ/m².
 99. A method as recited inclaim 95, comprising: activating said first and second bonding surfacesprior to said bonding step.
 100. A method as recited in claim 95,comprising: polishing said first and second bonding surfaces; andetching said first and second bonding surfaces after said polishing toactivate said first and second bonding surfaces.
 101. A method asrecited in claim 95, comprising: converting bonding by-products to aspecies capable of being absorbed by or diffusing away from said bondingsurfaces during said bonding step.
 102. A method as recited in claim 95,comprising: forming said first bonding surface as a surface of a firstsemiconductor wafer having devices formed therein; and forming saidsecond bonding surface as a surface of a second semiconductor waferhaving devices formed therein.
 103. A method as recited in claim 102,wherein one of said first and second wafers comprises a substrate, saidmethod comprising: removing a substantial portion of said one of saidfirst and second wafers.
 104. A method as recited in claim 102,comprising: interconnecting devices in said first and second wafers.105. A method as recited in claim 95, comprising: forming a firstinsulating layer on a first wafer containing electrical devices;polishing said first insulating layer to form said first bondingsurface; forming a second insulating layer on a second wafer containingelectrical devices; and polishing said second oxide layer to form saidsecond bonding surface.
 106. A method as recited in claim 95,comprising: forming a first insulating layer on a first wafer containingelectrical devices and having an irregular surface topology; polishingsaid first insulating layer to form said first bonding surface; forminga second insulating layer on a second wafer containing electricaldevices and having an irregular surface topology; and polishing saidsecond oxide layer to form said second bonding surface.
 107. A bondeddevice, comprising: a first material having a first etched bondingsurface; and a second material having a second etched bonding surfacedirectly bonded to said first bonding surface at room temperature havinga bonding strength of at least 500 to 2000 mJ/m².
 108. A device asrecited in claim 107, comprising: said first and second bonding surfacesbeing activated and terminated with a desired bonding species.
 109. Adevice as recited in claim 108, wherein said desired species comprise: amonolayer of one of a desired atom and a desired molecule on saidbonding surface.
 110. A device as recited in claim 108, wherein saiddesired species comprise at least one of a silanol group, an NH₂ group,a fluorine group and an HF group.
 111. A device as recited in claim 107,comprising: said first and second bonding surfaces each having adefective region located proximate to said first and second bondingsurfaces, respectively.
 112. A device as recited in claim 107, wherein:said first material comprises a surface of a first semiconductor waferhaving devices formed therein; and said second material comprises asurface of a second semiconductor wafer having devices formed therein.113. A device as recited in claim 112, wherein one of said first andsecond wafers comprises a device region after removing a substantialportion of a substrate of said one of said first and second wafers. 114.A device as recited in claim 112, comprising: devices in said first andsecond wafers being interconnected.
 115. A device as recited in claim112, comprising: said first and second wafers being differenttechnologies.
 116. A device as recited in claim 107, wherein: one ofsaid first and second wafers comprises an integrated circuit.
 117. Adevice as recited in claim 116, comprising: devices in said first andsecond wafers being interconnected.
 118. A device as recited in claim116, comprising: said first and second wafers having an irregularsurface topology.
 119. A device as recited in claim 107, wherein: saidfirst material comprises a first wafer containing electrical devices andhaving a first non-planar surface; and said first bonding surfacecomprises a polished and etched deposited oxide layer on said firstnon-planar surface.
 120. A device as recited in claim 119, wherein: saidsecond material comprises a second wafer containing electrical devicesand having a second non-planar surface; and said second bonding surfacecomprises a polished, planarized and etched deposited oxide layer onsaid second non-planar surface.
 121. A method as recited in claim 107,wherein: said first material comprises a first wafer containingelectrical devices and having a first surface with irregular topology;and said first bonding surface comprises a polished, planarized andetched deposited oxide layer on said first surface.
 122. A method asrecited in claim 121, comprising: said second material comprises asecond wafer containing electrical devices and having a second surfacewith irregular topology; and said second bonding surface comprises apolished, planarized and etched deposited oxide layer on said secondsurface.
 123. A bonded device, comprising: a first material having afirst etched and activated bonding surface terminated with a firstdesired bonding species; and a second material having a second etchedand activated bonding surface terminated with a second desired bondingspecies bonded to said first bonding surface at room temperature.
 124. Adevice as recited in claim 123, wherein said species comprise at leastone of a silanol group, an NH₂ group, a fluorine group and an HF group.125. A device as recited in claim 123, comprising: said first and secondbonding surfaces each having a defective region located proximate tosaid surfaces.
 126. A device as recited in claim 123, wherein saiddesired species comprises: a monolayer of one of a desired atom and adesired molecule on said bonding surface.
 127. A device as recited inclaim 123, comprising: said second bonding surface bonded to said firstbonding surface at room temperature having a bonding strength of atleast 500 to 2000 mJ/m².
 128. A device as recited in claim 123, wherein:said first bonding surface comprises a surface of a first semiconductorwafer having devices formed therein; and said second bonding surfacecomprises a surface of a second semiconductor wafer having devicesformed therein.
 129. A device as recited in claim 123, wherein one ofsaid first and second wafers comprises a device region after removing asubstantial portion of a substrate of said one of said first and secondwafers.
 130. A device as recited in claim 123, comprising: devices insaid first and second wafers being interconnected.
 131. A device asrecited in claim 123, comprising: said first and second wafers beingdifferent technologies.
 132. A device as recited in claim 123, wherein:one of said first and second wafers comprises an integrated circuit.133. A device as recited in claim 123, comprising: devices in said firstand second wafers being interconnected.
 134. A device as recited inclaim 123, wherein: said first material comprises a first wafercontaining electrical devices and having a first non-planar surface; andsaid first bonding surface comprises a polished and etched depositedoxide layer on said first non-planar surface.
 135. A device as recitedin claim 134, wherein: said second material comprises a second wafercontaining electrical devices and having a second non-planar surface;and said second bonding surface comprises a polished, planarized andetched deposited oxide layer on said second non-planar surface.
 136. Amethod as recited in claim 123, wherein: said first material comprises afirst wafer containing electrical devices and having a first surfacewith irregular topology; and said first bonding surface comprises apolished, planarized and etched deposited oxide layer on said firstsurface.
 137. A method as recited in claim 123, wherein: said secondmaterial comprises a second wafer containing electrical devices andhaving a second surface with irregular topology; and said second bondingsurface comprises a polished, planarized and etched deposited oxidelayer on said second surface.